FDMQ8403 n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation FDMQ8403 rev.c2 www.fairchildsemi.com 1 july 2012 FDMQ8403 greenbridge tm series of high-effici ency bridge rectifiers n-channel powertrench ? mosfet 100 v, 6 a, 110 m features ? max r ds(on) = 110 m at v gs = 10 v, i d = 3 a ? max r ds(on) = 175 m at v gs = 6 v, i d = 2.4 a ? substantial efficiency benefit in pd solutions ? rohs compliant general description this quad mosfet solution provid es ten-fold improvement in power dissipation over diode bridge. application ? high-efficiency bridge rectifiers bottom mlp 4.5x5 top 4 3 2 1 9 10 11 12 5 6 8 7 s3 s3 g3 d3/s4 d1/d4 g4 s2 s2 g2 d1/d4 g1 s1/d2 q4 q3 q1 q2 s2 s1/d2 g2 s2 d1/d4 g1 s3 d3/s4 g3 s3 d1/d4 g4 pin 1 s1/ d2 d1/d4 d3/ s4 mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous (package limited) t c = 25 c 6 a -continuous (silicon limited) t c = 25 c 9 -continuous t a = 25 c (note 1a) 3.1 -pulsed 12 p d power dissipation t c = 25 c 17 w power dissipation t a = 25 c (note 1a) 1.9 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 65 c/w r ja thermal resistance, junction to ambient (note 1b) 135 device marking device package reel size tape width quantity FDMQ8403 FDMQ8403 mlp 4.5x5 13 ?? 12 mm 3000 units
FDMQ8403 n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation FDMQ8403 rev.c2 www.fairchildsemi.com 2 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 100 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 72 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v 1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a22.84v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -8 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 3 a 85 110 m v gs = 6 v, i d = 2.4 a 115 175 v gs = 10 v, i d = 3 a, t j = 125 c 147 191 g fs forward transconductance v ds = 10 v, i d = 3 a 6 s c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1 mhz 162 215 pf c oss output capacitance 43 60 pf c rss reverse transfer capacitance 2.6 5 pf t d(on) turn-on delay time v dd = 50 v, i d = 3 a, v gs = 10 v, r gen = 6 4.1 10 ns t r rise time 1.2 10 ns t d(off) turn-off delay time 7.2 15 ns t f fall time 1.8 10 ns q g total gate charge v gs = 0 v to 10 v v dd = 50 v, i d = 3 a 35nc q g total gate charge v gs = 0 v to 5 v 1.7 3 nc q gs gate to source charge 0.9 nc q gd gate to drain ?miller? charge 0.8 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 3 a (note 2) 0.86 1.3 v t rr reverse recovery time i f = 3 a, di/dt = 100 a/ s 33 53 ns q rr reverse recovery charge 23 37 nc notes : 1. r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. a. 65 c/w when mounted on a 1 in 2 pad of 2 oz copper. the board designed q1+q3 or q2+q4. b. 135 c/w when mounted on a minimum pad of 2 oz copper. the board designed q1+q3 or q2+q4.
FDMQ8403 n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation FDMQ8403 rev.c2 www.fairchildsemi.com 3 typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 3 6 9 12 v gs = 7 v v gs = 10 v v ds , drain to source voltage (v) i d , drain current (a) v gs = 5 v v gs = 6 v v gs = 8 v pulse duration = 80 p s duty cycle = 0.5% max on region characteristics f i g u r e 2 . 03691 2 0 1 2 3 4 5 v gs = 8 v v gs = 10 v v gs = 7 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 6 v v gs = 5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i d = 3 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 45678910 0 100 200 300 400 t j = 125 o c i d = 3 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 234567 0 3 6 9 12 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 20 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMQ8403 n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation FDMQ8403 rev.c2 www.fairchildsemi.com 4 figure 7. 0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 10 i d = 3 a v dd = 75 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 50 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. forward bias safe operating area 0.1 1 10 100 300 0.005 0.01 0.1 1 10 20 100 us 10 s 10 ms dc 1 s 100 ms 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 135 o c/w t a = 25 o c figure 10. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.5 1 10 100 500 single pulse r t ja = 135 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation figure 11. 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 2 single pulse r t ja = 135 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to- ambient transient thermal response curve typical characteristics t j = 25 c unless otherwise noted
FDMQ8403 n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation FDMQ8403 rev.c2 www.fairchildsemi.com 5 dimensional outlin e and pad layout
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